A distributed and scalable architecture for packet processing

Growth of network line speeds and needs for new services in routers have led to the emergence of new generation of fast and scalable devices for packet processing, called network processors. In this paper, we propose a distributed model for packet processing, which is appropriate for network processors. In this model, the systems are extended to small networks of some basic connected nodes. Architecture of connections and topology of networks is the most important challenging task facing the designer. The proposed architecture contains a special instruction set devised for network environments. The architecture can be easily scaled and redesigned in functionality, instructions, memory and I/O system.