Title :
Threshold voltage and DIBL variability modeling for SRAM and analog MOSFETs
Author :
Damrongplasit, Nattapol ; Zamudio, Luis ; Balasubramanian, Sriram
Author_Institution :
EECS Dept., Univ. of California, Berkeley, CA, USA
Abstract :
A physically-based variability model is developed to explain threshold voltage (VT) and drain induced barrier lowering (DIBL) variations, and their correlations. Inputs to the model rely on forward (F) and reverse (R) data of measured transistor pair mismatch. Positionally asymmetric and symmetric random dopant fluctuation components of VT and DIBL variability are identified for SRAMs and analog devices from a 32nm HKMG technology and their correlations explained.
Keywords :
MOSFET; SRAM chips; transistors; DIBL variability modeling; DIBL variations; HKMG technology; SRAM; analog MOSFET; analog devices; asymmetric random dopant fluctuation components; drain induced barrier lowering variations; size 32 nm; symmetric random dopant fluctuation components; threshold voltage; Correlation; Data models; Mathematical model; Random access memory; Resource description framework; Semiconductor process modeling; Transistors;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242524
