Finite Field Multiplication Using Reordered Normal Basis Multiplier

We present in this paper affine linear and nonlinear techniques for design space exploration of the finite-field multiplication using reordered normal basis. Fifteen basic designs are possible using these linear techniques that are in close agreement with the results previously published using ad-hoc techniques. However, the major contribution of this paper is the introduction of nonlinear techniques to allow the designer to control the workload per processor and also control the communication requirements between processors. We present also models for the performance of processor arrays implementing the finite field multiplier. Performance includes system area, delay and power consumption. The main parameters affecting performance include the number of bits processed in parallel per processor and the hardware details such as how much each performance parameters depend on the number of bits being processed in parallel.