Title :
Scheduling of conditional process graphs for the synthesis of embedded systems
Author :
Eles, Petru ; Kuchcinski, Krzysztof ; Peng, Zebo ; Doboli, Alexa ; Pop, Paul
Author_Institution :
Dept. of Comput. & Inf. Sci., Linkoping Univ., Sweden
Abstract :
We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared buses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach
Keywords :
computer architecture; data flow graphs; processor scheduling; real-time systems; ASIC; architecture; conditional process graph; control flow; data flow; delay minimization; embedded system; heuristic; processor; scheduling; shared bus; synthesis; Embedded system;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655847
