DocumentCode :
2645343
Title :
A formally verified system for logic synthesis
Author :
Aagaard, Mark ; Leeser, Miriam
Author_Institution :
Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
fYear :
1991
fDate :
14-16 Oct 1991
Firstpage :
346
Lastpage :
350
Abstract :
The correctness of a logic synthesis system is implemented and proved. The algorithm is based on the weak division algorithm for Boolean simplification previously presented. The implementation is in the programming language ML; and the proof is in the Nuprl proof development system. This study begins with a proof of the algorithm previously presented and extends it to a level of detail sufficient for proving the implementation of the system. In the process of developing the proof many definitions presented in previous accounts of the algorithms were clarified, and several errors in the implementation were discovered. The result is that the designs generated by the implementation can be claimed to be correct by construction, since the correctness of the system was proven
Keywords :
Boolean functions; formal specification; logic CAD; Boolean simplification; Nuprl proof development system; correctness; errors; formally verified system; implementation; logic synthesis; programming language ML; weak division algorithm; Algorithm design and analysis; Boolean algebra; Boolean functions; Circuit synthesis; Computer languages; Hardware; High level synthesis; Logic programming; Process design; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
Type :
conf
DOI :
10.1109/ICCD.1991.139915
Filename :
139915
Link To Document :
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