DocumentCode
2645462
Title
4.0–4.8 Gbps XDR memory channel for graphics intensive consumer applications
Author
Secker, David ; Nakabayashi, Yoshie ; Lu, Yi ; Vaidyanath, Arun ; Kollipara, Gnanadeep ; Yeung, Philip ; Yip, Tsunwai Gary
Author_Institution
Rambus Inc., Los Altos, CA, USA
fYear
2011
fDate
9-12 Jan. 2011
Firstpage
777
Lastpage
778
Abstract
A 3.2 Gbps XDR™ memory channel has been optimized to achieve a bit rate of 4.8 Gbps. The 24-bit wide memory interface can deliver an aggregate data bandwidth of 14.4 GB/s to support graphics intensive consumer applications such as high refresh rate 3D digital TV. The optimized high performance channel is also designed to satisfy the low-cost constraint of consumer electronics by using wirebond packaging for the SoC and 4-layer PCB.
Keywords
DRAM chips; consumer electronics; printed circuits; system-on-chip; 3D digital TV; 4-layer PCB; SoC; XDR memory channel; bit rate 3.2 Gbit/s; bit rate 4 Gbit/s to 4.8 Gbit/s; consumer electronics; graphic intensive consumer applications; wirebond packaging; Consumer electronics; Consumer products; Graphics; Performance evaluation; Production; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location
Las Vegas, NV
ISSN
2158-3994
Print_ISBN
978-1-4244-8711-0
Type
conf
DOI
10.1109/ICCE.2011.5722858
Filename
5722858
Link To Document