DocumentCode
2645548
Title
Functional scan chain testing
Author
Chang, D. ; Lee, M.T.-C. ; Cheng, K.-T. ; Marek-Sadowska, M.
Author_Institution
Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
fYear
1998
fDate
23-26 Feb. 1998
Firstpage
278
Lastpage
283
Abstract
Functional scan chains are scan chains that have scan paths through a circuit´s functional logic and flip-flops. Establishing functional scan paths by test point insertion (TPI) has been shown to be an effective technique to reduce the scan overhead. However, once the scan chain is allowed to go through functional logic, the traditional alternating test sequence is no longer enough to ensure the correctness of the scan chain. We identify the faults that affect the functional scan chain, and show a methodology to find tests for these faults. Our results have the number of undetected faults at only 0.006% of the total number of faults, or 0.022% of the faults affecting the scan chain.
Keywords
automatic testing; flip-flops; logic testing; sequential circuits; ATPG; fault detection; flip-flops; functional logic; functional scan chain testing; functional scan paths; sequential fault simulation; test point insertion; Automatic test pattern generation; Circuit faults; Circuit testing; Design for testability; Flip-flops; Logic circuits; Logic testing; Sequential analysis; Sequential circuits; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris, France
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655868
Filename
655868
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