DocumentCode
2645666
Title
Timing analysis and optimization of a high-performance CMOS processor chipset
Author
Fassnacht, Uwe ; Schietke, Juergen
Author_Institution
IBM Entwicklung GmbH, Boeblingen, Germany
fYear
1998
fDate
23-26 Feb 1998
Firstpage
325
Lastpage
331
Abstract
We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server-Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results
Keywords
CMOS digital integrated circuits; circuit CAD; circuit analysis computing; circuit optimisation; delays; high level synthesis; timing; CMOS processor chipset; IBM S/390 Parallel Enterprise Server; gates; high-performance processor chipset; interconnects; optimization methodology; timing analysis; timing modeling; Analytical models; CMOS process; Clocks; Integrated circuit interconnections; Libraries; Logic; Mathematics; Optimization methods; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655876
Filename
655876
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