DocumentCode :
2645743
Title :
An energy-conscious exploration methodology for reconfigurable DSPs
Author :
Rabaey, Jan ; Wan, Marlene
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
1998
fDate :
23-26 Feb 1998
Firstpage :
341
Lastpage :
342
Abstract :
As the “system-on-a-chip” concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a variety of the macromodules (micro-processors, DSPs, programmable logic and embedded memories) are being reported by a number of companies. Most of these systems target the embedded market where speed, area, and power requirements are paramount, and a balance between hardware and software implementation is needed. Reconfigurable computing devices have recently emerged as one of the major alternative implementation approaches, addressing most of the requirements outlined above
Keywords :
circuit CAD; digital signal processing chips; high level synthesis; reconfigurable architectures; CAD; energy-conscious exploration methodology; macromodules; reconfigurable DSPs; Computer architecture; Digital signal processing; Electronics packaging; Energy efficiency; Field programmable gate arrays; Kernel; Multimedia systems; Partitioning algorithms; Personal digital assistants; Predictive models;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
Type :
conf
DOI :
10.1109/DATE.1998.655879
Filename :
655879
Link To Document :
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