DocumentCode :
2645749
Title :
Multiple fault detection and location in WSI baseline interconnection networks
Author :
Feng, C. ; Huang, W.-K. ; Lombardi, F.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear :
1990
fDate :
23-25 Jan 1990
Firstpage :
145
Lastpage :
151
Abstract :
Presents an approach for the full diagnosis (detection and location) of baseline interconnection networks implemented in WSI. A multiple fault model as applicable to production of these devices, is assumed. This implies that a totally exhaustive combinatorial fault model is used in the analysis. It is proved that the maximum number of tests for detecting multiple faults (i.e. 2(1+log2N), where N is the number of inputs/outputs), can be used to locate and identify multiple faulty switching elements provided that no intermittent and/or transient behaviour is present, i.e. using the definition of no logically undefined and no undetermined outputs are present. The proposed diagnostic technique is based on a process which reveals the switching state of each element on a stage by stage basis using the test set. No additional hardware is therefore required. The proposed technique can be efficiently used in the manufacturing of complex interconnection networks using advanced integration techniques such as WSI
Keywords :
VLSI; electronic switching systems; fault location; integrated circuit testing; multiprocessor interconnection networks; WSI baseline interconnection networks; detecting multiple faults; diagnostic technique; exhaustive combinatorial fault model; full diagnosis; identify multiple faulty switching elements; maximum number of tests; multiple fault detection; multiple fault location; multiple fault model; stage by stage basis; test set; Computer networks; Computer science; Electrical fault detection; Fault detection; Fault diagnosis; Hardware; Intelligent networks; Logic testing; Multiprocessor interconnection networks; Partial response channels;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
Type :
conf
DOI :
10.1109/ICWSI.1990.63895
Filename :
63895
Link To Document :
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