DocumentCode
2646361
Title
Behavioral modeling of a phase locked look
Author
Phanse, Abhijit ; Shirani, Ramin ; Rasmussen, Roy ; Mendel, Robi ; Yuan, J.S.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
1996
fDate
25-27 Jun 1996
Firstpage
400
Lastpage
404
Abstract
In this paper a methodology for modeling a Phase-Locked-Loop (PLL) has been presented. A behavioral model for the PLL was developed using an Analog Hardware Description Language (AHDL). This behavioral model is accurate with respect to SPICE simulations and provides a speed-up of 1600X over SPICE. The behavioral model was used to simulate the jitter in the generated clock during phase lock and evaluate the effect of the mismatches in the circuit on the jitter
Keywords
hardware description languages; jitter; phase locked loops; AHDL; Analog Hardware Description Language; behavioral model; circuit mismatch; clock; jitter; phase locked look; simulation; Circuit simulation; Clocks; Delay; Frequency synthesizers; Hardware design languages; Jitter; Phase detection; Phase frequency detector; Phase locked loops; SPICE;
fLanguage
English
Publisher
ieee
Conference_Titel
Southcon/96. Conference Record
Conference_Location
Orlando, FL
ISSN
1087-8785
Print_ISBN
0-7803-3268-7
Type
conf
DOI
10.1109/SOUTHC.1996.535101
Filename
535101
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