• DocumentCode
    2646670
  • Title

    Finding heap-bounds for hardware synthesis

  • Author

    Cook, B. ; Gupta, A. ; Magill, S. ; Rybalchenko, A. ; Simsa, J. ; Singh, S. ; Vafeiadis, V.

  • fYear
    2009
  • fDate
    15-18 Nov. 2009
  • Firstpage
    205
  • Lastpage
    212
  • Abstract
    Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during all executions. This bound can depend on the generic parameters to the program, i.e., program inputs that are instantiated at synthesis time. We propose a constraint based method for the discovery of memory usage bounds, which leads to the first-known C-to-gates hardware synthesis supporting programs with non-trivial use of dynamically allocated memory, e.g., linked lists maintained with malloc and free. We illustrate the practicality of our tool on a range of examples.
  • Keywords
    constraint handling; hardware-software codesign; tree data structures; C-to-gates hardware synthesis; constraint based method; data structure; dynamic allocated memory; hardware synthesis; heap bound; memory usage bound; program generic parameter; Acceleration; Circuit synthesis; Concrete; Costs; Data structures; Hardware; Productivity; Programming profession; Tree data structures; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods in Computer-Aided Design, 2009. FMCAD 2009
  • Conference_Location
    Austin, TX
  • Print_ISBN
    978-1-4244-4966-8
  • Electronic_ISBN
    978-1-4244-4966-8
  • Type

    conf

  • DOI
    10.1109/FMCAD.2009.5351120
  • Filename
    5351120