Design of a systolic pattern matcher for Nanomagnet Logic

Nanomagnet Logic (NML) is widely considered to be one of the promising for “beyond-CMOS” nanoscale architectures. So far only relatively simple circuits (nanomagnetic logic gates and adders) have been studied experimentally and in simulations. Here we investigate the possibility of building larger-scale computing devices from out-of-plane NML. We designed a systolic pattern matcher circuit that is in principle scalable to arbitrary number of nanomagnets and can match arbitrarily long patterns in an incoming data stream. The design of this systolic architecture for NML makes an important step toward large-scale devices.