Switching response modeling of the CMOS inverter for sub-micron devices

Author

Bisdounis, L. ; Nikolaidis, S. ; Koufopavlou, O. ; Goutis, C.

Author_Institution

VLSI Design Lab., Patras Univ., Greece

fYear

1998

fDate

23-26 Feb 1998

Firstpage

729

Lastpage

735

Abstract

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations

Keywords

CMOS logic circuits; SPICE; capacitance; circuit analysis computing; delays; logic CAD; logic gates; CMOS inverter; SPICE simulations; gate-to-drain coupling capacitance; input waveform slopes; inverter design characteristics; load capacitance; output waveform; propagation delay; short-circuit current; sub-micron devices; switching response modeling; Capacitance; Circuit simulation; Delay; Differential equations; Inverters; Physics computing; SPICE; Semiconductor device modeling; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655939

Filename

655939