A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration

Author

Zhang, Weicheng ; Dai, Xuan ; Jin, Jing ; Zhou, Jianjun

Author_Institution

Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1161

Lastpage

1164

Abstract

A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2 Â¿s according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling.

Keywords

calibration; digital phase locked loops; phase detectors; Simulink behavior simulation; adaptive bandwidth algorithm; calibration; digital frequency presetting module; digital phase-frequency detector; fast-settling ADPLL architecture; fast-settling all digital phase-locked-loop; frequency tuning word presetting; locking detector; time 2 mus; time domain behavior modeling; Bandwidth; Calibration; Digital filters; Error correction; IIR filters; Phase detection; Phase frequency detector; Phase locked loops; Phased arrays; Tuning; adaptive bandwidth; all-digital phase-locked loop (ADPLL); behavior model; fast-settling;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351165

Filename

5351165