DocumentCode
2647539
Title
Effects of switch failure on soft-configurable WSI yield
Author
Blatt, Miriam
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
1990
fDate
23-25 Jan 1990
Firstpage
152
Lastpage
159
Abstract
A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield
Keywords
CMOS integrated circuits; VLSI; fault tolerant computing; integrated circuit technology; integrated memory circuits; random-access storage; redundancy; Monte Carlo simulation; circuit yields; fault tolerant switch network; pipelined memory system; soft-configurable WSI yield; switch failure effects; switch yield; system model; wafer yield prediction; Circuit faults; Clocks; Costs; Decoding; Detectors; Protection; Redundancy; Switches; Voting; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9013-5
Type
conf
DOI
10.1109/ICWSI.1990.63896
Filename
63896
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