A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology

Author

Tan, Min

Author_Institution

Nat. Labs. of Analog Integrated Circuits, China Electron. Technol. Group Corp. (CETC), Chongqing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1185

Lastpage

1188

Abstract

An adaptively biased low-dropout regulator (LDO) in standard CMOS process technology is presented. By designing the poles and zeros carefully and utilizing the adaptive biasing technique, this LDO provides high stability, good line regulation as well as fast transient response, even with zero ESR off-chip compensation capacitor.

Keywords

CMOS integrated circuits; poles and zeros; transient response; voltage regulators; CMOS technology; adaptive biasing technique; low-dropout regulator; poles and zeros; transient response; zero ESR off-chip compensation capacitor; CMOS process; CMOS technology; Capacitors; Circuit stability; Frequency; Paramagnetic resonance; Poles and zeros; Power transistors; Regulators; Voltage; ESR; Low-dropout; adaptively biased; loop-stability;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351178

Filename

5351178

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2647564