Design of 16-bit 400MSPS current steering D/A converter

Author

Dongbing, Fu ; Dongmei, Zhu ; Shutao, Zhou ; Kaicheng, Li

Author_Institution

Nat. Labs. of Analog Integrated Circuits, Sichuan Inst. of Solid-state Circuits, Chongqing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1189

Lastpage

1192

Abstract

In this study, design of a 16-bit, 400MSPS high-speed high-resolution current steering D/A converter is described. With pipelined thermometer decoding, multi-stage synchronous latch, current-source matching array design, two-stage active cascade design, and current switch nonlinear capacitor bootstrapping compensation technologies, DAC dynamic performances at high frequency are improved. The DAC uses the design in 0.25 um CMOS process technology. Its die size is 4.84 mm Ã— 4.9 mm. High-frequency broadband SFDR>63 dBc@Fout=(331/1024) Ã— 400 MHz & F_sample =400 MHz.

Keywords

CMOS digital integrated circuits; digital-analogue conversion; integrated circuit design; 400MSPS current steering D/A converter; CMOS process technology; current switch nonlinear capacitor bootstrapping compensation; current-source matching array design; die size; high-frequency broadband SFDR; multistage synchronous latch; pipelined thermometer decoding; size 0.25 mum; two-stage active cascade design; CMOS technology; Capacitance; Decoding; Integrated circuit technology; Latches; Logic circuits; Solid state circuits; Switches; Switching circuits; Synchronization; Current-Steering DAC; SFDR; active cascode; dynamic linearity; matching;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351181

Filename

5351181