DCCB and SCC based fast circuit partition algorithm for parallel SPICE simulation

With the rapid scale growing of VLSI circuits, simulation speed and efficiency of CAD tool SPICE have turned out to be a bottleneck. Real VLSI circuit design simulation becomes unbearably time-consuming and urgent is the need to increase its efficiency. The emergence and thriving of multi-core systems in recent years offer a promising solution strategy to this problem. Circuit partition is required to these strategies, but traditional partition algorithms encounter difficulties when facing VLSI circuits for parallel simulation. This paper presents an efficient circuit partition algorithm specially designed for VLSI circuit partition and parallel simulation. The algorithm is established on recognizing DCCB and SCC. Our algorithm shows preferable solution quality and speedup for real experimental circuit designs compared with traditional ones.