Title :
Low power microprocessors for comparative study on bus architecture and multiplexer architecture
Author :
Komatsu, Satoshi ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
Decreasing capacitance of bus lines is one of the effective ways to reduce whole power dissipation of LSIs. In this paper we compare microprocessors designed based on a bus architecture and a multiplexer architecture in terms of power dissipation and delay time. Through implementation of a test chip, the multiplexer architecture is effective to reduce power dissipation by about 30%
Keywords :
computer architecture; delays; large scale integration; microprocessor chips; LSIs; bus architecture; delay time; low power microprocessors; multiplexer architecture; power dissipation; test chip; Capacitance; Circuits; Clocks; Delay effects; Microprocessors; Multiplexing; Power dissipation; Testing; Very large scale integration; Wiring;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669484
