An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration

Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to a user´s program. A method is presented for improving the performance of many computationally intensive tasks by extracting information at compile-time to synthesize new operations that augment the functionality of a core processor. The newly synthesized operations are targeted to RAM-based reconfigurable logic located within the processor. A proof-of-concept system called PLADO, consisting of a C configuration compiler and a hardware platform, is presented. Computation and performance results confirm the concept viability, and demonstrate significant speed-up