DocumentCode :
2648409
Title :
A new electrothermally-aware methodology for full-chip temperature optimization
Author :
Dong, Gang ; Leng, Peng ; Chai, Changchun ; Yang, Yintang
Author_Institution :
Microelectron. Inst., Xidian Univ., Xi´´an, China
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
1268
Lastpage :
1271
Abstract :
Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. The main idea is that characteristics of temperature distribution can be improved dramatically by a certain given delay penalty. As an example, based on HotSpot, the optimization for AMD Athlon 64 processor in 90-nm technology is given in the paper. Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced.
Keywords :
circuit optimisation; thermal management (packaging); delay penalty; electrothermal coupling; electrothermally-aware methodology; full-chip temperature optimization; temperature distribution; CMOS technology; Delay; Electrothermal effects; Heat transfer; Integrated circuit interconnections; Optimization methods; Repeaters; Resistance heating; Temperature; Thermal resistance; Electrothermal coupling; Full chip; Optimization; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351222
Filename :
5351222
Link To Document :
بازگشت