Design of AMBA APB bridge with reset controller for efficient power consumption

In this paper, one of AMBA (Advanced Microcontroller Bus Architecture) known as AMBA APB (Advanced Peripheral Bus) is designed which provides minimum power consumption and low bandwidth. For this, an APB Bridge with Reset Controller design has been implemented in Verilog language. Reset controller introduces a reset signal BnRES during Power-on Reset (POReset) conditions so that propagation of metastable values can be eliminated and glitches can be avoided. Power report shows that the various power components contribute in the total power consumption by APB bridge architecture. As the result of this paper: Bridge under POReset conditions, On-chip total power consumption is 9.52%, Hierarchy power consumption is 29.12% and dynamic supply power consumption is 28.89% less than Bridge under no PORset conditions. Hence, Bridge can be providing efficient utilization of power when it is designed under Power-on Reset conditions. The methodology adopted for the paper is Verilog language which is used to design finite state machine models and test benches. For modeling and simulation of APB Bridge and Reset Controller ModelSim Version 10.3 is used. Xilinx-ISE design suite, version 13.4 is used for synthesis and power reports. Power comparisons between AMBA APB Bridge with Power-on Reset conditions and without Power-on Reset conditions are also shown in table and graph at the end of the paper for developing a better understanding.