Response-pipelined CAM chips - Building blocks for large associated arrays

The authors introduce the architecture of a new type of fully parallel content addressable memory chips that serve as building blocks for large associated arrays. These new chips can be easily cascaded to increase the logical word size or the number of words and yet allow the search rate to be maintained constant irrespective of the logical word size or word count. Prototype CMOS implementations of the architecture have been tested and evaluated and demonstrated significant speedups compared to other existing associative hardware