Reconfigurable hardware implementation of host-based IDS

Author

Sato, Tomoaki ; Fukase, Masaaki

Author_Institution

Fac. of Social Inf., Sapporo Gakuin Univ., Ebetsu, Japan

Volume

2

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

849

Abstract

Host-based IDS installed individually to each host computer has been useful to supplement network-based IDS (intrusion detection system). However, host-based IDS so far developed lacks real-time response due to software implementation, and thus it has poor ability to dynamically analyze packet. In order to add the ability of real-time response with strong security, we have proposed the hardware implementation of host-based IDS built into NIC (network interface card). The hardware of host-based IDS has been designed by using wave-pipeline technique and implemented by using reconfigurable hardware, FPGA (field programmable gate array). This has achieved the fairly high speed of 400MHz that supports 1-Gbps bandwidth by processing a few bits in parallel on to-day´s major bit-serial Ethernet.

Keywords

field programmable gate arrays; local area networks; safety systems; 400 MHz; FPGA; bit-serial Ethernet; field programmable gate array; host-based intrusion detection system; network interface card; real-time response; reconfigurable hardware implementation; wave-pipeline technique; Bandwidth; Computer network management; Computer networks; Computer security; Ethernet networks; Field programmable gate arrays; Hardware; Information security; Intrusion detection; Operating systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2003. APCC 2003. The 9th Asia-Pacific Conference on

Print_ISBN

0-7803-8114-9

Type

conf

DOI

10.1109/APCC.2003.1274480

Filename

1274480