Title :
Switch-level fault coverage analysis for switched-capacitor systems
Author :
Mir, S. ; Rueda, A. ; Vázquez, D. ; Huertas, J.L.
Author_Institution :
Inst. de Microelectron., Centro Nacional de Microelectron., Sevilla, Spain
Abstract :
An approach to test optimization in switched-capacitor systems based on fault simulation at switch-level is presented in this paper. The advantage of fault simulation at this granularity level is that it facilitates test integration as early as possible in the design of these systems. Due to their mixed-signal nature, both catastrophic and parametric faults must indeed be considered for test optimization. Adequate switch-level fault models are presented. Test stimuli and test measures can be selected as a function of fault coverage. The impact of design parameters such as switch resistance on fault coverage is studied and design parts of poor testability are located
Keywords :
VLSI; fault diagnosis; integrated circuit testing; mixed analogue-digital integrated circuits; switched capacitor networks; catastrophic faults; design parameters; fault simulation; granularity level; mixed-signal nature; parametric faults; switch resistance; switch-level fault coverage analysis; switched-capacitor systems; test integration; test optimization; test stimuli; Automatic testing; Capacitors; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit testing; Life testing; Switches; System testing; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655951
