Introduction to SystemVerilog and SystemC

Summary form only given. SystemVerilog is the third generation of the Verilog language standard. It is a significant and important extension of Verilog-2001, and it includes many features which are useful for high-level modeling and verification of large and complex designs. SystemC runs in a C++ development environment, allowing modeling and verification of both hardware and software within a common framework. Both languages have rich features in system-level modeling and verification. The tutorial will cover most part of SystemVerilog, including data types and structures, behavioral modeling, design hierarchy and interfaces, object-oriented coding, threads, randomization and coverage. SystemC is also covered, including modules, ports, interfaces, channels, etc.