Title :
FPGA for high-performance bit-serial pipeline datapath
Author :
Isshiki, Tsuyoshi ; Shimizugashira, Takenobu ; Ohta, Akihisa ; Amril, Imanuddin ; Kunieda, Hiroaki
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
In this paper, we introduce our work on the chip design of a new FPGA chip for high-performance bit-serial pipeline datapath which is customized both in the logic architecture and routing architecture. The chip consists of 200k transistors on 3.5 mm square substrate (excluding the IO pad area) using 0.5 μ 2-metal process technology. The estimated clock frequency is 156 MHz
Keywords :
field programmable gate arrays; logic design; 156 MHz; 2-metal process technology; FPGA; chip design; clock frequency; high-performance bit-serial pipeline datapath; logic architecture; routing architecture; Clocks; Data engineering; Field programmable gate arrays; Frequency estimation; Large-scale systems; Logic circuits; Logic design; Pins; Pipelines; Routing;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669490
