Title :
Geometry optimization of SiGe HBTs for noise performance of the monolithic Low noise amplifier
Author :
Shen, Pei ; Zhang, Wanrong ; Xie, Hongyun ; Jin, Dongyue
Author_Institution :
Coll. of Electron. Inf. & Control Eng., Beijing Univ. of Technol., Beijing, China
Abstract :
The influence of various geometry sizes of SiGe HBTs on noise performance of the monolithic Low noise amplifiers(LNAs) is investigated in this paper. Four types of LNAs using SiGe HBTs with different emitter widths, emitter lengths and emitter strip numbers are fabricated in a 0.35-¿m Si BiCMOS process technology. The die areas are only 0.2 mm2 due to the absence of inductors. The noise figure(NF), associated gain(GA) and the optimum source resistance(Rs,opt) of the LNAs are compared. Simplified analytical expressions of NF and Rs,opt are presented to give additional insight. Geometry scaling data show that the LNA using SiGe HBT with AE=4×40×4¿m2 has the minimum NF of 2.7dB, the maximum gain of 26.7dB and the optimum Rs,opt of nearly 50¿ compared to other devices geometries. These experiment results provide a guide of device geometry optimizing to develop monolithic LNA for lower noise application.
Keywords :
geometry; heterojunction bipolar transistors; low noise amplifiers; BiCMOS process technology; SiGe; SiGe HBT; associated gain; emitter length; emitter strip number; emitter width; geometry optimization; monolithic low noise amplifier; noise figure; noise performance; optimum source resistance; BiCMOS integrated circuits; Geometry; Germanium silicon alloys; Heterojunction bipolar transistors; Inductors; Low-noise amplifiers; Noise figure; Noise measurement; Silicon germanium; Strips; SiGe HBTs; low noise amplifier; noise figure;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351284
