Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design

The authors present a transformation technique, called node merging, on bit-level dependence graphs to systematically explore tradeoffs between area and various system performances, such as clock period, pipelining period, block pipelining period, computation time, and dynamic power dissipation to obtain optimal VLSI array processors for bit-level regular algorithms. By merging several DG nodes into one node, multi-bit level array processors can be designed using formal regular array synthesis methods thereby significantly reducing the number of pipelining registers required compared to bit-pipelined array processors. In general, delay paths within a node in bit-level dependence graphs are unbalanced, and the clock period is determined by the critical path delay. By merging nodes along noncritical paths, the authors improve computation time as well as VLSI area with a relatively small increase in clock period and pipelining period. They also expand the complexity of node functions enough to apply a meaningful logic optimization or performance enhancement using well-known logic synthesis tools such as SIS for even further improvement. Since the transformation results in a new DG, it can be easily combined with conventional VLSI array synthesis techniques for efficient bit-level array processor design. Therefore, the method provides an efficient way to explore a significantly broader design space in VLSI array processor design