A novel architecture for a decision-feedback equalizer using extended signal-digit feedback

A novel bit-level systolic array architecture for implementing a bit parallel decision-feedback equalizer (DFE) is presented. Core of the architecture is an array multiplier using redundant arithmetic in combination with bit-level feedback. The use of signal-digit (SD) circuitry allows one to feed back each digit as soon as it is available. So the recursive computation can be executed with the most significant digit first (MSD first). This way a very high data throughput rate for large wordlengths is achieved. The combination of two SD-digits to one feedback digit allows one to further increase the throughput. The nonlinear quantization operation of the DFE is implemented by a combination of a saturation- and an integer operation. The saturation is done by a MSD first saturation unit for redundant digits. The integer operation is implemented by removing the fractional part of the intermediate result. The error caused by removing the fractional part of a redundant number is compensated by a correction unit. For a second-order DFE with two complex coefficients a throughput of one sample every three clock cycles is accomplished. The clock period is 4.75 full adder delays. This throughput is constant for large wordlengths. The architecture can be extended easily to higher order filters