VLSI array synthesis for polynomial GCD computation

Polynomial GCD (greatest common divisor) finding is an important problem in algebraic computation, especially in decoding error correcting codes. The authors show a new systolic array structure for the polynomial GCD problem using a systematic array synthesis technique. The VLSI implementation of the array structure is area-efficient and achieves maximum throughput with pipelining. The dependency graph (DG) of the Euclid GCD algorithm is drawn using iterated polynomial division. The resulting DG is data-dependent and variable-sized. The authors consider the worst-case implementation to make the DG data-dependent and fixed-size, where data-dependences are hidden inside by introducing four different working modes in each DG node. This novel approach requires just a few additional multiplexors and can be generalized for other data-dependent and variable-sized computation. The authors then map the DG to a one-dimensional systolic array using a linear mapping. The new array structure has m₀ + n₀ + 1 processing elements, where m₀ and n₀ are degrees of two polynomials. It can find a GCD of any two polynomials of total degree less than or equal to m₀ + n₀. The block pipeline period is one, which means that it can start a new GCD computation immediately in the next cycle. Unlike the array of Brent and Kung, a pre-processing step for extracting a common factor Xⁱ is not necessary and the size of the processing element (PE) does not depend on m₀ and n₀. The authors extend this new array structure to the extended polynomial GCD algorithm, which is closely related to the decoding of BCH and Reed-Solomon codes. To verify the structure, they have used the VERILOG simulator, and implemented a 2 μ CMOS test chip