An optimal algo-tech-cuit for the knapsack problem

The authors first present a formal derivation and proof of correctness of a systolic array for the knapsack problem, an NP-complete problem whose dependency graph is not completely known statically. With q PEs, each with a fixed size memory, the arraystretch runs in Γ(mc/q), which gives optimal speedup of the algorithm. However, it has an intricate tag-based control mechanism which is difficult to implement, and the authors improve the architecture so that the control can be implemented with two simple counters and a few flip-flops. Cofficient loading is done with a multi-rate clock which avoids the need for shadow registers. The authors then explore the tradeoff between the number of PEs and memory size, α, using the expected running time of the algorithm as a cost measure and a register level model of VLSI. It is shown analytically how α may be chosen to optimize the total computation time, yielding an area time optimal circuit