Design of 16 bit digital filter used in delta-sigma A/D converter

Author

Zhaochun, Lu ; Xiaohong, Peng ; Wuchen, Wu ; Ligang, Hou ; Yong, He

Author_Institution

VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China

Volume

4

fYear

2010

fDate

16-18 April 2010

Abstract

A digital decimation filter used in Δ-Σ - ADC is designed and introduced in this paper. The designed filter has a multi-stage structure which is comprised of a stage CIC filter, two stage half-band filters, and a stage compensation filter. The CSD coding, “Hognenauer cut-off theory”, frequency response masking approach and some other techniques are used to improve the performance of the chip and reduce the chip area and power consumption. This downsampling filter is achieved by algorithm modeling using MATLAB and hardware implementation using Verilog HDL. The performance indicators raised are achieved.

Keywords

analogue-digital conversion; comb filters; digital filters; encoding; hardware description languages; 16 bit digital filter; CIC filter; CSD coding; Hognenauer cut off theory; MATLAB; Verilog HDL; chip area; delta sigma A/D converter; digital decimation filter; down sampling filter; frequency response masking; power consumption; stage compensation filter; two stage half band filters; Circuits; Digital filters; Encoding; Energy consumption; Finite impulse response filter; Frequency response; Hardware design languages; Low pass filters; Sampling methods; Transfer functions; □-Σ A/DC; CIC filter; digital decimation low-pass filter; frequency response masking; half-band filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6347-3

Type

conf

DOI

10.1109/ICCET.2010.5485455

Filename

5485455