Efficient architecture of a programmable block matching processor

An efficient VLSI architecture of a programmable block matching processor for the emulation of a wide spectrum of full search and reduced complexity search block matching algorithms is presented. Optimized efficiency is obtained by using a quadratic systolic array architecture with global accumulation, combined with a programmable meander-like data flow. Flexibility is further increased by cascadability and the possibility of parallel operation of several processors. The efficiency of the architecture is illustrated by comparison with corresponding application specific VLSI architectures for several block matching algorithms