Title :
The chip Verification method based on memory monitoring
Author :
Liu, Sheng ; Yang, Huanrong ; Li, Yong ; Chen, Shuming
Author_Institution :
Nat. Univ. of Defense Technol., Changsha, China
Abstract :
A verification method based on memory monitoring is proposed for harmonizing the execution of RTL simulator and system-level model (SLM) simulator, in the situation that the SLM is a `black-box´ to the designers. This method can quickly and efficiently find the differences of big benchmarks´ executing process between the RTL simulation and SLM simulation, and help the verification engineers rapidly finding the bugs in the RTL codes and speedup the accomplishment of verification.
Keywords :
circuit simulation; integrated circuit design; integrated circuit testing; RTL simulator; chip verification method; memory monitoring; system level model simulator; Benchmark testing; Chip scale packaging; Circuit testing; Computational modeling; Computer bugs; Computer errors; Computerized monitoring; Electronic mail; Registers; Synchronous generators; Error Checking; Memory Monitoring; Verification;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351303
