A 1D linearly expandable interconnection network performance analysis

The authors describe the design and evaluation of a linear interconnection network for the image processing parallel architecture GFLOPS. This is a SIMD/MIMD architecture which can treat a wide range of application from low level to high level. The different memory banks of this structure are connected to the processors through a one stage interconnection network. This network is linearly expandable and provides a direct access from each processor to a subset of memory banks. The evaluation has been performed in both synchronous and asynchronous modes, with both local and global communications. The authors have studied first several algorithms as a benchmark, and then they have performed random memory accesses to evaluate the general characteristics of the network