DocumentCode
2649802
Title
A low power 50 MHz FFT processor with cyclic extension and shaping filter
Author
Bickerstaff, M. ; Arivoli, T. ; Ryan, P.J. ; Weste, N. ; Skellern, D.
Author_Institution
Dept. of Electron., Macquarie Univ., Sydney, NSW, Australia
fYear
1998
fDate
10-13 Feb 1998
Firstpage
335
Lastpage
336
Abstract
This paper presents the architecture, design and implementation of a 16 point FFT processor for a high speed wireless local area network. The 110000-transistor chip is implemented in 0.6 μm TLM CMOS, operates worst case at 50 MHz at a supply voltage of 2.5 volts, and consumes 80 mW
Keywords
CMOS integrated circuits; digital signal processing chips; fast Fourier transforms; filters; wireless LAN; 0.6 μm TLM CMOS; cyclic extension; low power 50 MHz FFT processor; shaping filter; wireless local area network; CMOS process; CMOS technology; Character generation; Computer architecture; Design methodology; Digital signal processing chips; Filters; Hardware design languages; Modems; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669493
Filename
669493
Link To Document