The design of an architecture-aware 32-bit signed/unsigned multiplier

This paper gives a detailed analysis and design of a X86 instruction compatible 32-bit multiplier, which is a part of a 486DX2 like CISC microprocessor. First,Various forms of multiply instructions should be supported by this multiplier are listed and analyzed.The micro instruction modes possibly used are proposed. Combines with the micro architecture of this processor, makes a compromise between the execution unit and the control unit, and take bypass logic into consideration, we demonstrates a 3-pipeline signed and unsigned unified multiplier, which meets the requirements of different types of multiply instructions and different result valid occasions. By means of radix-4 booth method, with the study of the high bits of signed operands, the conventional 17 partial products are reduced to 16, resulting of compact structure. Results show that, the area of this design has a reduction of 11.6% and it takes up less than 12% of the total power consumed by the processor in full load mode.