Transparent memory BIST

Author

Karpovsky, M.G. ; Yarmolik, V.N.

Author_Institution

Dept. of Electr. Comput. & Syst. Eng., Boston Univ., MA, USA

fYear

1994

fDate

8-9 Aug 1994

Firstpage

106

Lastpage

111

Abstract

This paper presents a new methodology for testing of bit-oriented and word-oriented RAMs based on circular test sequences, which can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches. The proposed approach is a transparent BIST technique combined with on-line error detection, which preserves the initial contents of the memory after the test and provides a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. Our methodology is useful for embedded RAMs and MCM implemented RAMs

Keywords

automatic testing; built-in self test; error detection; fault diagnosis; integrated circuit testing; production testing; random-access storage; MCM implemented RAMs; bit-oriented RAMs; circular test sequences; embedded RAMs; error models; fault models; high fault coverage; online error detection; pattern sensitive faults; testing methodology; transparent memory BIST; word-oriented RAMs; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Educational institutions; Fault detection; Hardware; Pulp manufacturing; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397189

Filename

397189