Title :
On fault modeling and testing of content-addressable memories
Author :
Al-Assadi, W.K. ; Jayasumana, A.P. ; Malaiya, Y.K.
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model
Keywords :
content-addressable storage; fault diagnosis; integrated circuit testing; integrated memory circuits; memory architecture; CAM architecture; CAM chips; IC testing; associative memories; content-addressable memories; fault modeling; testing strategy; CADCAM; Computer aided manufacturing; Concurrent computing; Distributed computing; Impedance matching; Logic arrays; Memory management; Random access memory; Read-write memory; Testing;
Conference_Titel :
Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-6245-X
DOI :
10.1109/MTDT.1994.397193
