DocumentCode :
2650048
Title :
Coupling noise analysis technique using random walks
Author :
Miwa, Hitoshi ; Suzuki, Goro
Author_Institution :
Univ. of Kitakyushu, Fukuoka, Japan
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
754
Lastpage :
759
Abstract :
Random walk method has recently been proposed in signal integrity analysis such as power grid noise analysis. This paper proposes techniques to apply random walk method to signal noise analysis for the data path circuit containing non-linear buffers and coupling capacitors. In order to fix output voltages and currents of non-linear buffer outputs, relaxation process is employed. To analyze coupling noise of both aggressors and victims, relaxation process is also introduced. The walk reward sharing technique improves computational efficiency by 6.2 times. In coupling noise analysis of example circuit, average voltage error of the coupling noise was 1.34% in 60 analysis timesteps and 50% delay error was 0.66% compared to SPICE. To analyze one timestep, average CPU time is 67 (ms) and the number of walks is 20,100 in 60 analysis timesteps.
Keywords :
capacitors; circuit simulation; coupling capacitors; coupling noise analysis technique; data path circuit; nonlinear buffers; power grid noise analysis; random walks; relaxation process; reward sharing technique; signal integrity analysis; signal noise analysis; Capacitors; Circuit analysis; Circuit noise; Computational efficiency; Coupling circuits; Data analysis; Delay; Power grids; Signal analysis; Voltage; Cross talk noise; Monte Carlo; Random walk; transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351315
Filename :
5351315
Link To Document :
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