• DocumentCode
    2650065
  • Title

    Design of an active memory system for network applications

  • Author

    Asthana, Abhaya ; Cravatts, Mark ; Krzyzanowski, Paul

  • Author_Institution
    AT&T Bell Labs., Murray Hill, NJ, USA
  • fYear
    1994
  • fDate
    8-9 Aug 1994
  • Firstpage
    58
  • Lastpage
    63
  • Abstract
    We describe an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. A network or I/O subsystem is built using an interconnected ensemble of such memory logic pairs. A complex network processing task can now be distributed between a large number of small memory processors each doing a sub-task, while still retaining a transparent memory interface. We argue that active memory based processing enables more powerful, scalable and robust designs for storage and communications subsystems, that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year
  • Keywords
    CMOS memory circuits; data structures; memory architecture; multiport networks; semiconductor storage; SWIM; active memory system; backend port; complex network processing task; data manipulation operations; data structures; interconnected ensemble; memory logic pairs; multimedia; network applications; processing logic; structured wafer-based intelligent memory; transparent memory interface; wireless PCS systems; Complex networks; Data structures; Hardware; Intelligent structures; Logic; Multimedia systems; Personal communication networks; Robustness; Software systems; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-8186-6245-X
  • Type

    conf

  • DOI
    10.1109/MTDT.1994.397196
  • Filename
    397196