Energy efficient vedic multiplier design using LVCMOS and HSTL IO standard

In this project, we are using LVCMOS and HSTL IO standards in order to match the resistance of input and output line, input and output port and Vedic multiplier. The primary purpose of Impedance matching is to eliminate transmission line reflection. Now, impedance matching is used to increase the stability of device with the help of IO standard. Therefore, selection of energy efficient IO standard will increase the energy efficiency of design under consideration. LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) and HSTL (High Speed Transceiver Logic) are energy efficient IO standard. Energy efficient IO standards are used to decrease the power dissipation of Vedic multiplier. Then, we try to achieve more energy efficiency with different technology (40nm, 65nm, 90nm) based FPGA. There is 95.07%, and 63.7% leakage power reduction with HSTLII_D18 IO standard, when we migrate our design from Virtex-5 to Virtex-6, and Virtex-4 respectively. With the energy efficient LVCMOS18 IO standard, there is 94.64% 61.57% reduction in leakage power, when we migrate our design from Virtex-5 to Virtex-6 and Virtex-4.