Electrical failure analysis in high density DRAMs

Author

Chan, Adrian ; Lam, David ; Tan, Wilson ; Khim, Swee Yong

Author_Institution

Texas Instrum., Singapore

fYear

1994

fDate

8-9 Aug 1994

Firstpage

26

Lastpage

31

Abstract

As density and complexity increase, the search for new test and analysis techniques can impact the role of failure analysis especially in the correct identification of failure mechanisms for root cause fixes to ensure timely introduction of a new product in a relatively competitive market. Design for Testability (DFT) offers some flexibility in trying to meet the demands made on the production test and on the defect analyses by reducing the time per test and in helping to carry out some specific type of tests. This paper presents test results of investigations carried out with the help of some DFT tests on the 1-Megabit, 4-Megabit and 16-Megabit Dynamic Random Access Memories (DRAMs) to detect the cause of an electrical fault in more detail. Several case examples depicting this work are presented

Keywords

DRAM chips; VLSI; design for testability; fault diagnosis; integrated circuit testing; production testing; 1 to 16 Mbit; design for testability; electrical failure analysis; failure mechanisms; high density DRAMs; production test; time per test; Circuit faults; Circuit testing; Design for testability; Failure analysis; Instruments; Logic arrays; Monitoring; Production; Random access memory; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397201

Filename

397201