Title :
A self-diagnostic BIST memory design scheme
Author :
Tsung MO, Chin ; Len Lee, Chung ; Ching Wu, Wen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper proposes a BIST structure for embedded RAMs. The structure has the self-diagnostic capability with only a minimal overhead. It degrades a little on the speed performance of the embedded RAM. Two sets of test patterns, MARCH and CHECKERBOARD, which detect most of the memory faults, are adopted in the scheme. This self-diagnosis capability makes this RAM BIST scheme able to be incorporated for the embedded RAM self-repaired redundant design to increase its yield
Keywords :
SRAM chips; built-in self test; cellular arrays; circuit optimisation; fault diagnosis; integrated circuit yield; random-access storage; redundancy; CHECKERBOARD; MARCH; embedded RAMs; memory faults; minimal overhead; self-diagnostic BIST; self-repaired redundant design; speed performance; test patterns; yield; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Electrical fault detection; Fault detection; Random access memory; Read-write memory; Shift registers;
Conference_Titel :
Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-6245-X
DOI :
10.1109/MTDT.1994.397205
