Wireless built-in self-repair architectures for embedded RAMs

In order to reduce test and repair cost in advanced system-on-chip products, wireless built-in self-repair (BISR) techniques for embedded memories are proposed in this paper. The redundant memory is divided into spare rows, spare column group blocks, and spare words which are used to replace faulty cells in the main memory. Based on this redundancy architecture, a BISR scheme suitable for built-in implementation is proposed. According to simulation results, our techniques have higher repair rates and lower hardware overhead as compared with previous works. Finally, we integrated the proposed memory with BISR circuitry into the HOY wireless test system. Experimental results show that the hardware overhead (including the wireless interface modules) is only 0.39% for a 16 M-bit SRAM.