DocumentCode
2650686
Title
Analysis technique for systematic variation over whole shot and wafer at 45 nm process node
Author
Nakanishi, Jingo ; Notani, Hiromi ; Nakase, Yasunobu ; Shinohara, Hirofumi
Author_Institution
Design & Dev. Unit, Renesas Technol. Corp., Hyogo, Japan
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
585
Lastpage
588
Abstract
We propose a test structure for systematic variation measurement over the whole shot and wafer area at a 45 nm process node. With this structure, we found that the systematic variation had two kinds of site dependence, one is a wafer scale and the other is a shot scale component. Additionally, the Die-to-Die and Within-Die variations for any chip size are calculated. Then, the systematic variation component has the correlation length more than 16 mm. This shows that it is necessary to take into consideration the Within-Die variation according to the Die size.
Keywords
CMOS integrated circuits; integrated circuit testing; CMOS technology; correlation length; die-to-die variations; shot scale; size 45 nm; systematic variation measurement; test structure; wafer area; wafer scale; within-die variations; Area measurement; Chip scale packaging; Circuit testing; MOSFETs; Manufacturing processes; Process control; Semiconductor device measurement; Size measurement; System testing; Timing; Device variation; Within-Die and Die-to-Die variation; analysis of Within-Wafer; test structure for systematic variation measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351353
Filename
5351353
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