ISTA: An embedded architecture for post-silicon validation in processors

In this paper, we present a new architecture for post-silicon validation called ISTA, internal signal trace analysis. The objective of ISTA is to give the bug location, including the occurring time and place, during post-silicon validation. ISTA consists of an error detector, several hardware probes called signal trace probes (STPs) which are embedded in the chip, and an off-chip instruction set simulator (ISS). During post-silicon validation, the information acquired by STPs is analyzed to detect whether an error has occurred and if occurred, give the occurring time and place of the bug. ISTA offers us the ability to detect errors and locate bugs at real-time, fault-tolerant debug, great debug flexibility, and some other advantages. Synthesis results show that the hardware cost of ISTA is at a reasonable level.