Title :
Automatic configuration generation for a SOC co-verification technology based FPGA functional test system
Author :
Ruan, A.W. ; Liao, Y.B. ; Li, P. ; Li, W. ; Li, W.C.
Author_Institution :
State Key Lab. of Electron. Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A FPGA-under-test has to be configured before it is tested. However, traditional configuration for a FPGA-under-test is time consuming due to the fact that the configuration has to be conducted manually many times until each resource of FPGA is not left behind. Automatic configuration generation for a FPGA-under-test implemented by an in-house SOC co-verification technology based FPGA functional test system is proposed and presented in the paper. Software side will dispatch configuration order to hardware side, while hardware side will produce configuration timing and inform software side the FPGA-under-test is available. Configuration bit-stream data will be transmitted to hardware side. Depending on the information of status register of configuration module, software part can determine whether configuration has been implemented or not. Experimental result demonstrates that it only takes about 1.5 seconds for one configuration.
Keywords :
field programmable gate arrays; logic testing; system-on-chip; FPGA functional test system; SOC coverification technology; automatic configuration generation; field programmable gate array; system-on-a-chip coverification technology; Automatic testing; Circuit testing; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Logic testing; Paper technology; Programmable logic arrays; System testing; Timing; FPGA; SOC co-verification; configuration generation; test;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351358
